1. Field of the Invention
The present invention relates generally to a semiconductor process, and more specifically, to a semiconductor process that polishes a plurality of gate structures of different vertical heights at the same time by changing the polishing selectivity of a chemical mechanical polishing process or by adding an etching process.
2. Description of the Prior Art
In modern CMOS integrated circuits, progress in production techniques has enabled the size of components to be scaled down to deep-submicron sizes for both improving the performance of the integrated circuits and increasing the operating speed. Some problems, however, particularly involving reliability, will occur with the decrease in size of components. Other processes should therefore be integrated in the semiconductor processes in order to solve these problems.
For example, in order to reduce the sheet resistance of the source/drain region and the gate of CMOS components, a self-aligned silicide (Salicide) process is provided. The self-aligned silicide (Salicide) process is performed by covering a metal layer on a substrate and gates after the gates and the source/drain regions alongside the gates are formed. The metal layer is then heated to transform it to a silicide, and the unreacted metal layer is removed.
Because the salicide is selectively disposed on a needed portion of the substrate and the gates, a salicide block (self-aligned silicide block or SAB) is formed in the areas not covered by salicide to prevent salicide coverage occurring before the metal layer is covered. When there are two gate structures, one gate structure needs to be covered by salicide while the other one does not, so a salicide block will cover the gate structure that does not need to be covered by salicide. After the process is performed, the two gate structures will have different thicknesses, so the interdielectric layer material that covers the thinner gate structure will remain even after a polishing process is performed. On the other hand, if the interdielectric layer material is entirely removed, the thicker gate structure will be over-etched or over-polished; this results in the vertical height of the gate structure being hard to be controlled, which affects the inner structure of the gate structure and thereby reduces the electrical performance.